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ATmega128
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
W hen the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the
TAP controller is in reset. W hen programmed and the JTD bit in MCUCSR is cleared, the TAP
input signals are internally pulled high and the JTAG is enabled for Boundary-scan and program-
ming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP
controller is not shifting data, and must therefore be connected to a pull-up resistor or other
hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The
device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect External Reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the Reset line
are used in the application.
Figure 120. Block Diagram
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI
TDO
TCK
TAP
CONTROLLER
JTAG PROGRAMMING
INTERFACE
TMS
AVR CPU
INSTRUCTION
REGISTER
FLASH
MEMORY
Address
Data
INTERNAL
SCAN
CHAIN
PC
Instruction
ID
REGISTER
BREAKPOINT
M
U
X
BYPASS
REGISTER
UNIT
FLOW CONTROL
UNIT
DIGITAL
PERIPHERAL
UNITS
BREAKPOINT
SCAN CHAIN
JTAG / AVR CORE
ADDRESS
DECODER
OCD STATUS
COMMUNICATION
INTERFACE
AND CONTROL
I/O PORT n
247
2467X–AVR–06/11
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